Analyst Ming-Chi Kuo has echoed different reviews that Apple is anticipated to make use of a brand new chip packaging know-how within the A20 chip, which is able to debut within the iPhone 18 subsequent 12 months. His report focuses on suppliers for chip packaging supplies, moderately than the advantages of the brand new course of. We heard the identical from analyst Jeff Pu a pair months in the past.
If you purchase an iPhone 16 as we speak, the A19 chip inside is a fairly large and sophisticated monolithic “system on a chip.” It’s obtained the CPU, GPU, Neural Engine, video and audio encoders and decoders, and a bunch of different little stuff all on one huge advanced piece of silicon with round 30 billion transistors. Many chips are made on a giant silicon disk (known as a wafer) after which packaged up and reduce into particular person A19 chips, known as “dies.”
However the RAM is just not on the identical piece of silicon. RAM is often manufactured utilizing totally different silicon processes, on totally different huge wafers, reduce into their very own dies. Then the RAM is mixed with the large SoC by connecting the 2 collectively utilizing one other piece of silicon, known as an interposer.
That is finished as a result of the manufacturing processes that produces SRAM effectively is totally different than what produces logic effectively. However with a brand new TSMC know-how known as “Wafer-Stage Multi-Chip Module (WMCM) packaging,” which may all change.
This course of will make it attainable for Apple to construct a giant monolithic chip that contains the RAM on the identical die because the CPU, GPU, Neural Engine, media encoders, and so forth. If the present rumors are appropriate, this could be 12GB of RAM, however the course of doesn’t require any certain quantity. Rumors level to the iPhone 18 as the primary gadget to make use of the brand new chip, and the iPhone Fold may be a candidate.
On-die RAM could simplify the manufacturing course of, requiring fewer steps than the present RAM-on-interposer setup. However the profit for customers is the potential to have very extensive and quick RAM interfaces, making entry to RAM nearly as quick as a high-level SRAM cache. This might drastically enhance efficiency in conditions which might be restricted by reminiscence bandwidth, comparable to high-performance 3D graphics or sure AI functions.
It might additionally permit for higher energy administration, permitting the SoC with built-in RAM to make use of much less energy than the present setup with RAM hooked up on an interposer. This will enhance battery life, however battery life is an element of many various elements just like the show, wi-fi radios, storage, and extra.
